The present invention generally relates to electronic logic gates comprised of transistors. More specifically, it relates to an improved method and system for identifying dynamic NAND or NOR gates from a netlist having output nodes, supply voltages along with their opposite supply voltages, and FETs with their connectivity.
Computer aided design (CAD) systems that design electronic circuits, often referred to as Electronic CAD (ECAD) systems, assist in the design of electronic circuits by providing a user with a set of software tools running on a digital computer with a graphical display device. The design process has now become so difficult that the current generation of integrated circuit (IC) chips, particularly in the case of very large scale integrated chips (VLSI), often cannot be designed without the help of ECAD systems. ECAD tools are ideally suited to performing tasks implemented in the circuit design process as they can break down large, complicated circuits into a plurality of circuits of relatively simpler functionality. The ECAD tools can then iteratively lay out these much simpler circuits and achieve the desired overall design of the desired large complicated circuit.
In performing a circuit design task, the ECAD tool generally allows for a user to schematically create and/or edit circuit designs by graphically placing and connecting circuit components, which may be represented as objects by the ECAD tool. The ECAD tool performs calculational circuit design and evaluation tasks for the schematic circuit, such as optimizing the circuit, testing the circuit through simulation modeling, and the like. As represented by the ECAD tool, the circuit may comprise a plurality of xe2x80x9cnets,xe2x80x9d with each net representing a connection between the terminals of two transistors. A net may also be referred to as a signal. An ECAD tool also typically generates a xe2x80x9cnetlist,xe2x80x9d which is a list of a group of logically related nets, including connectivity data for each. The netlist may be in the form of a database. Also, the netlist may describe a multiplicity of nets that can number into the millions for VLSI related tasks. As a result, netlists can be of enormous size and complexity.
Different types or sub-tools of an ECAD tool may be used in IC design/evaluation tasks. In particular, ECAD tools can be used to identify the topology of a design stored on a netlist by identifying constituent field effect transistors (xe2x80x9cFETsxe2x80x9d) that comprise logic gates. FETs are transistors with a region of donor material with two terminals called the xe2x80x9csourcexe2x80x9d and the xe2x80x9cdrainxe2x80x9d. Between the source and the drain is an adjoining region of acceptor material between, called the xe2x80x9cgatexe2x80x9d. The voltage between the gate and the substrate controls the current flow between the source and the drain by depleting the donor region of its charge carriers to a greater or lesser extent. A design may have thousands or millions of FETs on the chip, which makes it impractical to identify the topologies without the use of automated methods. This is especially true with a netlist having dynamic logic gates. Unlike static logic gates, the circuit outputs change dynamically with dynamic logic gates, which are usually but not necessarily controlled by clock signals.
There are currently some existing tools for identifying dynamic circuits from a netlist, but they are generally cumbersome and limited. This is so because they require not only the topologies of the chip, but also knowledge of the clock signals that drive the FETs. More specifically, users must indicate all the clock signals before the tools can automatically identify the logic gates from the netlist. Thus, there is a need for an improved method for identifying topologies of chip designs.
The present invention is directed to an improved method and system for identifying the topologies of a chip design. More specifically, it relates to an improved method and system for identifying dynamic NAND or NOR gates from a netlist having output nodes, supply voltages along with their opposite supply voltages, and FETs with their connectivity. A NAND logic gate is a logic gate representing the Boolean function which is true unless both its arguments are true. A NOR logic gate is a logic gate representing the Boolean function which is true if none of its inputs are true and false otherwise.
The present invention provides a method that includes the steps of selecting an output node from the netlist, identifying FETs, having at least one branch, that are connected directly to the selected output node but not connected directly to the supply voltage, verifying that the branch(es) of the identified FETs define a dynamic logic gate, and identifying either a NAND gate or a NOR gate for the dynamic logic gate.
The present invention also provides a computer system that includes a storage medium, a processor for executing a program stored on the storage medium for selectively identifying dynamic NAND or NOR gates from potential output nodes, supply voltages with their opposite supply voltage, and FETs with their connectivity, wherein the program includes a set of instructions for: selecting an output node from the netlist, identifying FETs having at least one branch that are connected directly to the selected output node but not connected directly to the supply voltage, verifying that the branch(es) of the identified FETs define a dynamic logic gate, and identifying either a NAND gate or a NOR gate for the dynamic logic gate.